Electronic design automation (EDA) tools are often used to generate a detailed design of a semiconductor circuit. Computer-implemented tools such as computer-aided design (CAD) tools are often used to carry out the design flow. Many of the operations may be implemented as software running on computer servers and/or workstations.
A typical digital design flow may involve generating a system specification that provides design parameters for the semiconductor circuit to one or more of the EDA tools. A circuit implementing the system specification may then be generated manually or automatically (such as by using ready-made IP functions). The circuit may be entered by a hardware description language (such as Verilog, VHDL, or any other hardware description language (HDL)), or by other means. In a logic synthesis operation, an abstract form of desired circuit behavior (typically a register transfer level (RTL) description or behavioral description) is turned into a design implementation in terms of logic gates. In a verification operation, the netlist output by the logic synthesis operation is verified for functionality against the circuit design specification. A physical implementation of the netlist may then be performed, including an analysis to verify functionality, timing and performance across predetermined or user-specified ranges of process, voltage, and temperature parameters.
As integrated circuits become more and more complex, the timing behavior exhibited by certain circuit blocks becomes ever more critical to understand and evaluate. Generally, timing analysis involves measuring the propagation delay of signals through every timing path through a given system. During logic synthesis and place-and-route, timing analysis guides the optimization procedures. Analog circuits generally can't be optimized in the same way that logical circuits are optimized.
Conventionally, designers utilizing a digital design flow employ static timing analysis for digital circuit blocks. The static analysis includes a limited evaluation of propagation delays independent of the circuit block inputs and system data. While this method may operate well for digital circuit blocks, attempting to apply such a static timing analysis method to analog circuit blocks may be problematic, especially for analog parallel multi-state drivers that may exhibit intentionally different timing behavior depending on how the input signals are programmed.
Accordingly, what is needed are methods, systems and associated apparatus that allow for improved static timing analyses in digital design flows for analog circuit blocks such as parallel multi-state drivers.